The invention relates to analog-to-digital converters that are useful in digital audio applications, particularly to a monolithic integrated circuit dual analog-to-digital converter that utilizes only a single successive approximation register.
An integrated circuit analog-to-digital converter (ADC) component that is extensively used in digital audio applications such as digital stereo amplifiers, tape recorder/players, and the like is the assignee's model PCM78 16 bit hybrid integrated circuit analog-to-digital converter. The PCM78 is a 16 bit ADC which, in response to an analog audio input signal, produces a continuous stream of serial digital data that very accurately represents the audio input signals. The analog signals can be subsequently accurately reconstructed from the serial digital data. The assignee's PCM78 16 bit analog-to-digital converter is a hybrid integrated circuit that includes two monolithic chips, the first being manufactured using bipolar processing techniques and including a comparator and a voltage reference circuit. (It is necessary to provide very stable, low noise analog reference voltages to implement high accuracy analog-to-digital converters suitable for digital audio applications.) The second chip is manufactured using CMOS technology and includes a successive approximation register and control logic. Users of the PCM78 often use a single PCM78, two external sample and hold circuits (one for the left channel and one for the right channel), and multiplexing circuitry coupling the two sample and hold circuit outputs to a single PCM78. One problem with this circuit configuration is that it can operate at only half the sample rat that could be achieved if two PCM78's are used. The lower sampling rate necessitates the use of more expensive antialiasing filters at the inputs of the sample and hold circuits and also results in a lower ADC signal to noise ratio because less averaging of the noise can be achieved. If digital delays in the two sample and hold control circuits are not precisely matched, there will be a timing skew in the desired co-phase sampling of the two audio inputs. For portable applications, the relatively high power consumed by the bipolar portion of the PCM78 can be problematic.
Although the PCM78 has been commercially very successful, there is a need to significantly reduce the cost of its function. At the present time, it is necessary to utilize two such 16 bit ADC's if it is desired to provide separate analog-to-digital conversion functions for both the right audio channel signal and the left audio channel signal in order to make a digital stereo amplifier or the like. Until now no one has attempted to provide two analog-to-digital converters with the 16 bit or greater accuracy that is needed for high fidelity digital audio applications on a single integrated circuit chip, because this would make the chip larger than presently is economically feasible. Although 16 bit ADC accuracy is generally considered adequate for most digital audio applications, there is a market demand for even higher fidelity "digital audio" reproduction. There is a market demand for simultaneous sampling (referred to as co-phase sampling) of right and left channel audio signals prior to analog-to-digital conversion, instead of multiplexing between right and left channels, which has been the usual previous technique.
It would be desirable to be able to use less expensive antialiasing filters in a digital audio circuit. This can be achieved if the sampling rate is increased. Prior analog-to-digital circuits have not been able to operate at a sufficiently high oversampling rate to allow much less expensive filtering circuitry to be used. The prior analog-to-digital converters used for digital audio applications generally have been of the successive approximation type.
In some prior systems, two ADC's have been used to allow faster sampling rates so that less expensive anti-aliasing filters can be used. In such systems, the "left channel" ADC and the "right channel" ADC each have included a separate 16 bit analog-to-digital converter with its own successive approximation register (SAR).
Accurate comparators are required in a successive approximation analog-to-digital converter for digital audio applications. The comparators need to operate at high speed, with low noise and low input offset errors. In the past, auto-zeroing techniques have been used to reduce input offset errors in bipolar differential amplifiers and in CMOS differential amplifiers. If auto-zeroing circuitry is used, it usually is connected to the output of the first amplifier stage. It should be appreciated that an object in the design of a high speed, high gain amplifying or pre-amplifying stage of the kind used in a comparator is to achieve precise, high speed operation with minimum noise, and minimum offset. To achieve this, it may be considered desirable to perform an auto-zeroing function at the output of each amplifying stage of the amplifier. This may result in auto-zeroing MOSFETs introducing noise on the output conductors of that stage which, when "referred back" to the inputs, is reduced by the gain of that stage. Various techniques have been used to achieve the benefits of low noise, high speed operation, and low integrated circuit chip area. One approach is to provide a single differential amplifier stage with very high gain, with a source follower output stage and autozeroing at its outputs, but this does not result in high speed. Another possible approach is to provide multiple lower gain but higher speed stages and provide auto-zeroing between the various stages, in the hopes of obtaining low noise, high speed operation, but this does not provide low noise. Determining the best approach usually involves difficult design tradeoffs.
It would be desirable to provide an improved FET differential amplifier and/or an improved CMOS comparator that provides lower noise, higher speed, and lower input offset voltage and occupies less chip area than has yet been achieved in the art.